Asian Journal of Current Research

This work presents a transistor-level design and comparative evaluation of parallel prefix adders implemented using a 45 nm CMOS process. The study focuses on the optimization of fundamental prefix cells, namely white, grey, black and sum cells, through the combined use of transmission-gate logic and static CMOS techniques. The optimized cells are incorporated into the Brent–Kung adder architecture and simulated in Cadence Virtuoso at a supply voltage of 1 V and an operating frequency of 1 GHz. The full-custom implementation was selected instead of an FPGA- or synthesis-based approach to allow direct control over device dimensions, switching behavior and circuit-level performance parameters. The proposed design is compared with conventional CMOS-based Kogge–Stone, Ladner–Fischer, Han–Carlson and Brent–Kung adder architectures for 4-bit, 8-bit, 16-bit and 32-bit configurations. The evaluation considers propagation delay, average power consumption, power–delay product (PDP) and transistor count under an FO4 load condition. Simulation results show that the proposed transmission-gate-based Brent–Kung adder achieves lower power consumption and a reduced PDP across the evaluated bit widths. For the 32-bit configuration, the proposed architecture records a delay of 1.14 ns, power consumption of 41.62 µW and a PDP of 47.4468 fJ.Transistor-count analysis also indicates reductions of approximately 40.8%, 37.9%, 35.8% and 34.9% for the 4-bit, 8-bit, 16-bit and 32-bit implementations, respectively, compared with the conventional Brent–Kung adder. These results indicate that the proposed architecture provides an improved balance among speed, power dissipation and hardware complexity for energy-efficient arithmetic circuit design in nanoscale VLSI applications.