Asian Journal of Current Research

This paper presents a compact 14-transistor hybrid full adder for low-power and high-speed digital arithmetic applications in a 45 nm CMOS process. The proposed design combines CMOS logic with pass-transistor logic to reduce circuit complexity while preserving the required full adder functionality. The architecture is organised into three modules: an XOR/XNOR generation block, a SUM generation block, and a CARRY generation block. The XOR/XNOR module produces complementary intermediate signals, which are then processed by the SUM and CARRY modules to generate the final outputs. The circuit was designed and simulated in Cadence Virtuoso using the Spectre simulator at a 1 V supply voltage. Performance was evaluated using transistor count, propagation delay, average power consumption, and power-delay product as the main metrics. Under the stated simulation conditions, the proposed full adder uses 14 transistors and achieves a delay of 13.42 ps, an average power consumption of 0.448 µW, and a power-delay product of 6.01 × 10⁻¹⁸ J. Comparative analysis with selected previously reported hybrid full adders indicates that the proposed circuit provides lower transistor count and improved delay and power-delay product values within the same reported evaluation framework. The reduced number of transistors supports a compact implementation, while the hybrid logic arrangement contributes to efficient switching and signal generation. The design also maintains separate SUM and CARRY generation stages, supporting clear modular implementation for one-bit arithmetic operation. These findings suggest that the proposed 14-transistor hybrid full adder may be useful in arithmetic units where low power dissipation, reduced circuit complexity, and high-speed operation are important design considerations.