Dynamic On-resistance and Charge Trapping in Gallium Nitride Power Devices
Neha Singh *
Department of Electronics and Communication Engineering, Govind Ballabh Pant University of Agriculture and Technology, Pantnagar, Uttarakhand 263145, India.
Deep Sehgal
Semiconductor Laboratory (SCL), Ministry of Electronics and Information Technology (MeitY), Mohali, India.
*Author to whom correspondence should be addressed.
Abstract
Aims: This review examines how charge trapping and electrical stress history influence dynamic on-resistance in gallium nitride power devices and considers the implications for measurement and converter-loss estimation.
Study Design: A focused narrative review synthesising device-level mechanisms, pulsed and continuous-switching measurements, and converter-oriented interpretation.
Methodology: Published journal studies were compared according to device architecture, stress conditions, measurement timing, reported findings and limitations on transferring results. Targeted literature searches were updated on 8 August 2026. No new device experiments or pooled quantitative analysis were undertaken.
Findings: The reviewed evidence associates dynamic on-resistance with charge trapping in buffer, surface and gate-related regions, together with temperature and preceding bias conditions. Reported resistance changes depend on the applied blocking voltage, gate bias, pulse sequence, sampling delay and reference-resistance definition. Double-pulse tests reveal responses after defined stress intervals, whereas continuous-switching measurements examine the effects of repeated electrical histories. The relationship with voltage or switching frequency is not necessarily monotonic and cannot be assumed to be transferable between device architectures. Measurement artefacts and thermal effects can also influence the reported resistance ratio. Consequently, a single dynamic-resistance multiplier does not adequately represent all converter operating conditions.
Conclusion: Dynamic on-resistance should be characterised using reproducible, device-specific procedures that document electrical history, measurement uncertainty and thermal conditions. Converter-loss estimates should reflect the relevant current waveform and switching sequence rather than relying exclusively on static resistance values.
Keywords: Gallium nitride, high-electron-mobility transistors, dynamic on-resistance, charge trapping, current collapse, buffer trapping, gate instability, double-pulse testing, continuous switching, converter conduction loss