Asian Journal of Current Research

Design and Comparative Evaluation of Parallel Prefix Adders Using a 45 nm CMOS Process

Pallavi Chauhan — 2026-06-22

This work presents a transistor-level design and comparative evaluation of parallel prefix adders implemented using a 45 nm CMOS process. The study focuses on the optimization of fundamental prefix cells, namely white, grey, black and sum cells, through the combined use of transmission-gate logic and static CMOS techniques. The optimized cells are incorporated into the Brent–Kung adder architecture and simulated in Cadence Virtuoso at a supply voltage of 1 V and an operating frequency of 1 GHz. The full-custom implementation was selected instead of an FPGA- or synthesis-based approach to allow direct control over device dimensions, switching behavior and circuit-level performance parameters. The proposed design is compared with conventional CMOS-based Kogge–Stone, Ladner–Fischer, Han–Carlson and Brent–Kung adder architectures for 4-bit, 8-bit, 16-bit and 32-bit configurations. The evaluation considers propagation delay, average power consumption, power–delay product (PDP) and transistor count under an FO4 load condition. Simulation results show that the proposed transmission-gate-based Brent–Kung adder achieves lower power consumption and a reduced PDP across the evaluated bit widths. For the 32-bit configuration, the proposed architecture records a delay of 1.14 ns, power consumption of 41.62 µW and a PDP of 47.4468 fJ.Transistor-count analysis also indicates reductions of approximately 40.8%, 37.9%, 35.8% and 34.9% for the 4-bit, 8-bit, 16-bit and 32-bit implementations, respectively, compared with the conventional Brent–Kung adder. These results indicate that the proposed architecture provides an improved balance among speed, power dissipation and hardware complexity for energy-efficient arithmetic circuit design in nanoscale VLSI applications.

An Energy-Efficient 14-T Hybrid Full Adder with High-Speed Operation in a 45 nm CMOS Process

Shweta Bhandari — 2026-06-22

This paper presents a compact 14-transistor hybrid full adder for low-power and high-speed digital arithmetic applications in a 45 nm CMOS process. The proposed design combines CMOS logic with pass-transistor logic to reduce circuit complexity while preserving the required full adder functionality. The architecture is organised into three modules: an XOR/XNOR generation block, a SUM generation block, and a CARRY generation block. The XOR/XNOR module produces complementary intermediate signals, which are then processed by the SUM and CARRY modules to generate the final outputs. The circuit was designed and simulated in Cadence Virtuoso using the Spectre simulator at a 1 V supply voltage. Performance was evaluated using transistor count, propagation delay, average power consumption, and power-delay product as the main metrics. Under the stated simulation conditions, the proposed full adder uses 14 transistors and achieves a delay of 13.42 ps, an average power consumption of 0.448 µW, and a power-delay product of 6.01 × 10⁻¹⁸ J. Comparative analysis with selected previously reported hybrid full adders indicates that the proposed circuit provides lower transistor count and improved delay and power-delay product values within the same reported evaluation framework. The reduced number of transistors supports a compact implementation, while the hybrid logic arrangement contributes to efficient switching and signal generation. The design also maintains separate SUM and CARRY generation stages, supporting clear modular implementation for one-bit arithmetic operation. These findings suggest that the proposed 14-transistor hybrid full adder may be useful in arithmetic units where low power dissipation, reduced circuit complexity, and high-speed operation are important design considerations.

Harnessing Artificial Intelligence in Genomics for the Prevention of Recessive Disorders: An Overview

Jatin Dahiya — 2026-06-08

Recessive genetic disorders, frequently concealed within heterozygous carriers, reveal a substantial challenge in context of clinical genetics owing to their asymptomatic characteristics in carriers and the profound consequences when transmitted in a bi-allelic manner. These disorders contribute significantly to the global burden of inherited diseases, with prevalence influenced by ethnicity, population genetics, and consanguinity patterns. The emergence of next-generation sequencing has facilitated the accessibility of extensive genomic data; nonetheless, the intricacies of interpretation continue to present a significant impediment. The fields of artificial intelligence (AI) and machine learning are now transforming the genomic landscape by facilitating comprehensive analyses of genomic variants, amalgamating phenotype data, and forecasting disease risks with enhanced speed and precision. This review examines the contemporary AI-driven methodologies employed in the prevention of recessive disorders through carrier screening, embryo selection, and extensive population analyses. We reference recent advancements, including AI systems such as PhenIX, X rare, Deep Variant, and prioritization frameworks based on GPT-4. Additionally, we address ethical considerations, challenges pertaining to clinical translation, and the potential of generative artificial intelligence in the context of genetic counseling. By scrutinizing both the technical evolution and translational significance, this review positions artificial intelligence as an indispensable instrument in predictive and preventive genomic medicine. However, the integration of artificial intelligence in genomics is not without limitations, including algorithmic bias, data privacy concerns, and underrepresentation of diverse populations in training datasets. These challenges may affect diagnostic accuracy and equitable clinical implementation, underscoring the need for careful validation and ethical oversight.

A Comparative Review of Remaining Useful Life Modelling Approaches for Predictive Maintenance: Physics-based, Data-driven, and Hybrid Methods

Evans Addo — 2026-06-19

Predictive maintenance has become an important strategy for improving the reliability, safety, and operational efficiency of industrial systems. A central task in predictive maintenance is the estimation of Remaining Useful Life (RUL), which supports maintenance planning by predicting the time available before a component or system reaches a defined failure condition. This review provides a comparative discussion of major RUL modelling approaches used in predictive maintenance, with particular attention to physics-based, data-driven, and hybrid methods. Physics-based models use engineering knowledge and mathematical representations of degradation processes to generate interpretable predictions; however, their development depends on a detailed understanding of system behaviour and failure mechanisms. Data-driven models use historical and real-time sensor data to learn degradation patterns and have shown strong potential in complex industrial environments, particularly through machine learning and deep learning techniques. Their performance, however, often depends on the availability of sufficient labelled data and may be limited by poor interpretability. Hybrid models combine physical knowledge with data-driven learning to improve robustness, reliability, and practical applicability. The review also discusses transfer learning, explainable artificial intelligence, digital twins, and Industry 4.0 integration as emerging directions for RUL prediction. Key challenges identified include limited run-to-failure data, changing operating conditions, model scalability, uncertainty in predictions, and integration with industrial maintenance systems. Overall, the review indicates that no single modelling approach is universally suitable for all predictive maintenance applications. The selection of an appropriate RUL model should depend on data availability, domain knowledge, system complexity, interpretability requirements, and deployment conditions in practice.