FPGA-based Control Devices for Real-time Systems: A Critical Review of Design Trends, Challenges and Research Priorities
Naqaa Luqman Mohammed *
Engineering Technical College of Computer and AI, Northern Technical University, Mosul, Iraq.
*Author to whom correspondence should be addressed.
Abstract
Field-programmable gate arrays (FPGAs) have moved from peripheral glue logic to the computational core of demanding real-time control devices in power conversion, electrical drives, instrumentation, robotics and scientific facilities. The device class has also changed: contemporary parts combine programmable fabric with hardened processors, memory interfaces and communication blocks, so that the controller is now a heterogeneous system rather than a homogeneous array of look-up tables. This review critically evaluates the literature on FPGA-based control devices for real-time systems, covering architectural evolution, design-entry methodologies, control-algorithm realisation, timing determinism, dynamic reconfiguration, embedded learning-based functions, dependability, security and validation practice. Peer-reviewed journal literature published between 2007 and 21 July 2026 was identified through Crossref, CORE, the Directory of Open Access Journals, OpenAIRE and Europe PMC, supplemented by backward and forward citation searching, with every retained record verified against the digital object identifier registry. The synthesis indicates that the strongest evidence concerns algorithm-level acceleration: parallel hardware realisation reliably shortens the computational interval of model predictive, sliding-mode and observer-based control laws, enabling control strategies that were previously infeasible at short sampling periods. Evidence is substantially weaker for three classes of claim that appear frequently: that FPGA-based controllers are inherently more energy efficient than processor-based alternatives, that reported latency figures constitute real-time guarantees, and that dynamic partial reconfiguration is practical in deployed safety-relevant control loops. Comparative studies rarely equalise optimisation effort across platforms, timing evidence is usually observational rather than analytical, and dependability and security are treated as separate literatures that seldom inform control-device design. Priorities include standardised reporting for control-oriented hardware evaluation, analytical timing models for heterogeneous programmable platforms, and integrated treatment of reconfiguration, fault tolerance and trust within a single design methodology.
Keywords: Field-programmable gate array, real-time control, embedded systems, high-level synthesis, dynamic partial reconfiguration, system-on-chip, timing determinism, hardware-in-the-loop simulation